1. Field of the Invention
This invention relates to a drive circuit for a display apparatus, and more particularly to a drive circuit for a display apparatus which is capable of gray-scale display by means of amplitude modulation. In this specification, a matrix type liquid crystal display apparatus will be described as a typical example of a display apparatus, but this invention can also be applied to drive circuits for other types of display apparatus such as electroluminescent (EL) display apparatus and plasma display apparatus.
2. Description of the Prior Art
When driving a liquid crystal display (LCD) apparatus, since the speed of response of a liquid crystal is very slow as compared with a luminescent material used in a cathode ray tube (CRT) display apparatus, a special drive circuit is used. That is, in a drive circuit for an LCD apparatus, video signals which are sequentially sent are not immediately supplied to respective pixels, but the video signals are sampled for each of the respective pixels in one horizontal period and held for the horizontal period. The held video signals are output at the same time at the beginning of the next horizontal period, or at an appropriate point of time in the next horizontal period. After the output of video signal voltages to the respective pixels are begun, the signal voltages are held for a period of time sufficiently over the speed of response of the liquid crystal.
In order to hold the signal voltages, a prior art drive circuit utilizes capacitors. FIG. 16 shows a signal voltage output circuit (a source driver) for supplying drive voltages to a plurality of pixels (in this case, 120 pixels) on one scanning line selected by a scanning signal. A portion for the nth pixel of the source driver is shown in FIG. 17. The portion includes an analog switch SW.sub.1, an sampling capacitor C.sub.SMP, an analog switch SW.sub.2, a holding capacitor C.sub.H, and an output buffer amplifier A. The operation of the signal voltage output in the prior art will be described with reference to the circuit diagrams of FIGS. 16 and 17, and also to the signal timing chart of FIG. 18. Analog video signals v.sub.s to be input to the analog switches SW.sub.1 are sequentially sampled in accordance with sampling clock signals T.sub.SMP1 -T.sub.SMP120 which correspond to the respective 120 pixels on one scanning line selected by each horizontal synchronizing signal H.sub.syn. By this sampling, the sequential instantaneous voltages V.sub.SMP1 -V.sub.SMP120 of the video signals v.sub.s are applied to the corresponding sampling capacitors C.sub.SMP. The nth sampling capacitor C.sub.SMP is charged up to the value of the video signal voltage V.sub.SMPn corresponding to the nth pixel, and holds this value. The signal voltages V.sub.SMP1 -V.sub.SMP120 which are sequentially sampled and held in one horizontal period are transferred from the sampling capacitors C.sub.SMP to the holding capacitors C.sub.H for holding outputs, in response to an output pulse OE which is supplied to all of the analog switches SW.sub.2 at the same time. Then the signal voltages V.sub.SMP1 -V.sub.SMP120 are output to source lines O.sub.1 -O.sub.120 connected to the respective pixels through the buffer amplifiers A.
To the drive circuit described above, analog video signals are supplied. Such a drive circuit presents the following problems (A1) and (A2) when attempts are made to increase the size or improve the resolution of a liquid crystal panel.
(A1) When the charges in the sampling capacitors C.sub.SMP are transferred to the holding capacitors C.sub.H, the relationship between the voltage V.sub.H of the holding capacitor C.sub.H and the sampled voltage V.sub.SMP (the voltage of the sampling capacitor C.sub.SMP) is represented by expression (1) as follows: ##EQU1## Accordingly, in order that the voltage V.sub.H held by the holding capacitor C.sub.H is substantially equal to the sampled voltage V.sub.SMP, a condition of C.sub.SMP &gt;&gt;C.sub.H is required to be satisfied. That is, it is necessary to use the sampling capacitor C.sub.SMP of a large capacitance. However, if the capacitance of the sampling capacitor C.sub.SMP is too large, it is necessary to make the time for charging (i.e. a sampling period) longer. On the contrary, as the size of the LCD apparatus is made larger or the resolution is improved, the number of pixels corresponding to one horizontal period increases, thereby necessitating a sampling period to be shortened in reverse proportion. It can be seen that there is a limit to the increase in size or the improvement in resolution of the LCD apparatus.
(A2) In the drive circuit for e matrix type display apparatus, unlike the display in a CRT, analog video signals are sampled in accordance with a clock signal and displayed in pixels arranged in a matrix. At this time, since delays of signals in the drive circuit including delays in the bus lines is unavoidable, it is extremely difficult to accurately establish the sampling position for the analog video signals. Particularly, when displaying a computer graphic image in which the relationship between video signals and pixel addresses should be precisely defined, shift in the image display position, bleeding of the image, etc., due to signal delays in the drive system and deterioration of the frequency characteristics cause significant problems.
These problems which occur when using analog video signals are solved by using digital data as video signals. When video signals are supplied in the form of digital data, a drive circuit shown in FIGS. 19 and 20 is used. For the sake of simplicity, the video signal data is composed of 2 bits (D.sub.0, D.sub.1). That video signal data have four values 0-3, and a signal voltage applied to each pixel is any one of four levels V.sub.0 -V.sub.3. FIG. 19 ks a circuit diagram showing a digital source driver circuit corresponding to the analog source driver circuit shown in FIG. 16. The circuit diagram of FIG. 19 shows the entire source driver for supplying driving voltages to 120 pixels similar to that shown in FIG. 16. FIG. 20 shows a portion for the nth pixel in the circuit. The portion of the circuit comprises a D-type flip-flop (sampling memory) M.sub.SMP at a first stage and a flip-flop (holding memory) M.sub.H at a second stage which ere provided for the respective bits (D.sub.0, D.sub.1) of the video signal data, a decoder DEC, and analog switches ASW.sub.0 -ASW.sub.3 each of which is provided between corresponding one of four external voltage sources V.sub.0 -V.sub.3 and a source line O.sub.n. For the sampling of digital video signal data, various circuits may be used other than the D-type flip-flop.
The digital source driver operates as follows. The video signal data (D.sub.0, D.sub.1) are sampled at the rising of a sampling pulse T.sub.SMPn corresponding to the nth pixel, by the sampling memory M.sub.SMP. At the time when the sampling for one horizontal period is completed, an output pulse OE is fed to the holding memories M.sub.H. All the video signal data (D.sub.0, D.sub.1) held in the holding memories M.sub.H are simultaneously output to the respective decoders DEC. Each of the decoder DEC decodes the 2-bit video signal data (D.sub.0, D.sub.1). In accordance with the values (0 to 3), one of the analog switches ASW.sub.0 -ASW.sub.3 is conductive, and the corresponding one of the four external voltages V.sub.0 -V.sub.3 is output to the source line O.sub.n.
The source driver in which digital video signals are used for sampling can solve the problems (A1) and (A2) which arise when analog video signals are used for sampling. However, this source driver still has the following problems (D1) and (D2) to be solved.
(D1) With the increase in number of bits of digital video signal data, the size of each of memory cells, decoders, etc., constituting a drive circuit is drastically enlarged. Therefore, the size of a chip and the production cost are greatly increased.
(D2) When voltage sources supplied externally (V.sub.0 -V.sub.3 in FIGS. 19 and 20) are selected by using analog switches, the selected voltage source is directly connected to a source line of the liquid crystal panel and drives the source line. Accordingly, the circuit is required to have a performance capable of sufficiently driving the heavy load, i.e. the liquid crystal panel. This causes the production cost to increase. Especially, in the case where the number of gray-scale levels for image display is increased so that the number of bits of video signal data is increased, in the circuit of FIG. 19 (or FIG. 20), the required number of external voltage sources is increased by a power of 2. For example, when the video signal data is composed of 2 bits as in the circuit of FIG. 19 (or FIG. 20), the number of the external voltage source levels is 2.sup.2 =4. For 3-bit video signal data, the number of levels is 2.sup.3 =8, and for 4-bit, the number of levels is 2.sup.4 =16. In this manner, the number of levels is drastically increased. As mentioned above, when the number of external voltage sources is drastically increased with the increase in number of data bits, and moreover, each of the external voltage sources must drive the above-mentioned heavy load, the source device for the drive circuit becomes enormous.